1. Field of the Invention
This invention relates generally to a process for forming semiconductor die-to-substrate conductor interconnections and, more specifically, to a process for forming standardized bonding locations for varying die sizes, configurations, bond pad arrangements and circuitry, and a semiconductor die assembly formed therefrom.
2. State of the Art
The first integrated circuits became available in the late 1960s having a minimal number of circuits on each chip of silicon. These first components typically included aluminum or gold-based thin-film traces to integrate the active and passive devices embedded in the silicon. Since these first simple semiconductor devices, the circuit count per die has grown exponentially. In the early 1970s, bipolar logic chips had about 100 circuits and monolithic memory had 128 bits forming the first commercial, bipolar main memory. Since. then, the number of logic circuits has grown to over 10,000 per chip (bipolar) and one gigabit memory chips, with FET transistors replacing bipolar.
The active component or device integration and densification process in integrated circuits has motivated a continuous and ongoing migration of intercircuit wiring and connections from boards, cards, and modules to the chip itself. The surface of the chip, with its multilayer wiring, has become a microcosm of the conductor and insulator configurations that were common on previous multilayer printed circuit boards and multilayer ceramic packages. A logic chip with 700 circuits and three layers of wiring has approximately 5 m of aluminum wiring on a chip less than 5 mm square. There are over 17,000 via connections from level to level through a micron-tlhick insulator film of SiO.sub.2. Yet, the conductor capacity in the chip greatly lags behind the densification of the silicon devices. Most of the area of the chip (approximately two-thirds), still serves as a platform for the wiring.
Heretofore, serial wirebonding of one or two rows of bond pad input/outputs (I/Os) around the perimeter or down the center of the chip to leads and sometimes buses of a leadframe has satisfied the needs of most ceramic or plastic dual in-line packages. Automated wirebonding today is very fast, efficient, and reliable compared to the manual bonding of the 1960s. Wirebonding, however, appears to be yielding for some applications to TAB bonding, in which the density of perimeter connections can be doubled or tripled and all bonds made simultaneously. Solder-bumped connections have evolved into an area array or pattern configuration in which a large portion of the surface of the chip is covered with controlled collapse chip connections (C4s) for the highest possible I/O counts. Unlike wirebonding, C4 usually dictates solder bump formation on the active surface of the chip when the chip is in wafer forn. Typically, in such structures, a layer of silicon oxide, silicon nitride, or polyimide passivation must be formed over the final wiring level on the active surface of the chip before formation of the bumps. This has become a commonplace precaution to protect the fine wiring from corrosion and mechanical damage, even in advanced wirebonded chips.
Solder-bump interconnection was initiated in the early 1960s to eliminate the expense, unreliability, and low productivity of manual wirebonding. Whereas the initial, low-complexity, low circuit density chips typically required only peripheral contacts or bond pads, solder-bump technology has allowed considerable extendibility in I/O density as it progressed to full-population area arrays. Typically, C4s utilize solder bumps deposited on wettable metal pads on the chip and a matching footprint of solder wettable terminals at the ends of circuit traces carried by the substrate. The upside-down chip (commonly referred to as a "flip chip") is aligned to the substrate, and all joints are made, simultaneously by reflowing the solder. It is also known to employ conductive polymer bumps or polymers loaded with conductive particles in lieu of solder bumps in arrays. Fine pitch bump arrays have been generally termed "ball grid arrays," or "BGAs," in the art.
In addition to the densification of C4s or other conductive bumps on a given die (also interchangeably referred to in the art as a "chip"), technological advances in the art have decreased the overall size of semiconductor dice (for a given circuit density). Further, due to ongoing advances in circuit component design and fabrication technology, a given die may be "shrunk" one or more times during its commercial lifesl)an to enhance per-wafer yield, device speed and performance, and quality. In addition, similar dice from different manufacturers may be of different sizes and/or shapes, but are adaptable to use on the same printed circuit board or other conductor-carrying substrate. Consequently, the need to allow for varying sized dice for a given substrate has been recognized. For example, U.S. Pat. No. 5,168,345 discloses a substrate having a plurality of conductive leads arranged in a generally radial pattern to which dice of various sizes may be attached. Likewise, in U.S. Pat. No. 5,327,008, a universal leadframe is disclosed which is suitable for use with many different die sizes. In both of the foregoing patents, bond wires are employed to connect die bond pads to leadframe leads.
Such arrangements, however, are not practical for bump-type interconnections (flip-chip bonding) of dice having markedly different bond pad patterns thereon, due to the precise mutual locational requirements of the bump interconnections and the matching terminals or other connector structures on a substrate or other carrier. Thus, it would be advantageous to provide a bumped die to which a standardized array of terminals or trace ends of a substrate or other carrier such as a leadframe could be bonded, regardless of die size or bond pad pattern. Thus, a single substrate or leadframe conductor configuration might be employed to accommodate different generations of the same die or different dice altogether.